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19-0298; Rev 4; 5/96
KIT ATION EVALU ABLE AVAIL
6-Bit Quadrature Digitizer
_______________General Description
The MAX2101 6-bit quadrature digitizer combines quadrature demodulation with analog-to-digital conversion on a single bipolar silicon die. This unique RF-to-Bits TM function bridges the gap between existing RF downconverters and CMOS digital signal processors (DSPs). The MAX2101's simple receiver subsystem is designed for digital communications systems such as those used in DBS, TVRO, WLAN, and other applications. The MAX2101 accepts input signals from 400MHz to 700MHz and applies adjustable gain, providing at least 40dB of dynamic range. Each baseband is filtered by an on-chip, 5th-order Butterworth lowpass filter, or the user can select an external filter path. Baseband sample rate is 60Msps. The MAX2101 is available in a commercial temperature range, 100-pin MQFP package.
____________________________Features
o ADCs Provide Greater than 5.5 Effective Bits at fS = 60Msps, fIN = 15MHz o Fully Integrated Lowpass Filters with Externally Variable Bandwidth (10MHz to 30MHz) o 40dB Dynamic Range o Integrated VCO and Quadrature Generation Network for I/Q Demodulation o Divide-by-16 Prescaler for Oscillator PLL o Programmable Counter for Variable Sample Rates o Signal-Detection Function o Selectable Offset Binary or Twos-Complement Output Data Format o Automatic Baseband Offset Cancellation
MAX2101
________________________Applications
Recovery of PSK and QAM Modulated RF Carriers Direct-Broadcast Satellite (DBS) Systems Television Receive-Only (TVRO) Systems Cable Television (CATV) Systems Wireless Local Area Networks (WLANs)
______________Ordering Information
PART MAX2101CMQ TEMP. RANGE 0C to +70C PIN-PACKAGE 100 MQFP
__________________________________________________Typical Application Circuit
LOW-NOISE AMPLIFIER
X/KU BAND
H POLARIZATION V POLARIZATION
950MHz to 2000MHz LOCAL OSCILLATOR LOW-NOISE BLOCK LOCAL OSCILLATOR L-BAND DOWNCONVERTER
600MHz (NARROW BAND)
MATCHED FILTERS 0 QUADRATURE GENERATION 90 DIV-16 612MHz PHASE LOCKED
TMRF-to-Bits
CLOCK AND CARRIER RECOVERY
ERROR DETECTION AND CORRECTION
MISCELLANEOUS DSP
A/D CONVERSION DSP POST PROCESSING
MAX2101
is a registered trademark of Tektronix, Inc.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
6-Bit Quadrature Digitizer MAX2101
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Ranges (Note 1) VCC ...................................................................(-0.3V to +6.5V) VINA .....................................................................(VCCA + 0.3V) VIND ....................................................................(VCCD + 0.3V) Continuous Power Dissipation (TA = +70C) .......................1.6W Operating Temperature Range...............................0C to +70C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, <10sec)...........................+300C
Note 1: The digital control inputs are diode protected; however, permanent damage may occur on unconnected units under highenergy electrostatic fields. Keep unused units in conductive foam or shunt the terminals together. Discharge the conductive foam to the destination socket before insertion.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 4.75V to 5.25V, TA = +25C, unless otherwise noted.) PARAMETER Digital Supply Current ADC Supply Current RF Blocks Supply Current IF Port DC Dynamic Range IF Port Input Resistance AGC Input Voltage AGC Input Resistance AGC Input Capacitance AGC Range AGC Control Slope Variation AGC Control Input Bias Current Lowpass Filter Tune Input Resistance Lowpass Filter Tune Input Capacitance TNKA, TNKB Resonant Port Bias Voltage LO Resonant Port Input Resistance LO Resonant Port Input Capacitance LO Prescaler Output High (Note 3) LO Prescaler Output Low LO Prescaler Output Source Current LO Prescaler Output Sink Current Baseband Amplifier DC Gain Baseband Input--Input Capacitance Baseband Amplifier I/Q Offset Match (Note 4) Baseband Amplifier Offset Adjust Input Resistance SYMBOL ICCD ICCAD ICCRF VIF RIF VAGMIN VAGMAX RAGC CAGC AGCR SVAGC IAGC RILPF CILPF VLO RILO CILO VOH VOL IOH IOL AVBB CIBB VOFFBB ROFFBB (Note 2) LSB = 24mV, ENOPB = 0V, VFTUNE = VFTMIN to VFTMAX Voltage Range = 1V to 4V 10 (Note 2) 4.1V on complementary input (Note 2) (Note 2) RL = 1M, CL = 15pF RL = 1M, CL = 15pF RL = 1M, CL = 15pF, VO = 2.4V RL = 1M, CL = 15pF, VO = 0.5V 400 50 27 29 31 2 1.0 2.4 0.5 1 10 2 Variation dB/V Voltage range = 1V to 4V 10 2 3 20 (Note 2) 40 4:1 A k pF V k pF V V A A dB pF LSB k VIF = 100mV VIF = 0.5mV CONDITIONS VCCA, VCCO, VCCD, VCCC VCCAD VCCIF, VCC2, VCC1, VCCQ 0.5 40 1.0 2.3 50 MIN TYP MAX UNITS 102 80 170 100 75 1.5 2.9 100 2 mA mA mA mV V k pF dB DC SPECIFICATIONS (VGND = System Ground, VCCA = VCCD = 5.0V 5%)
2
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6-Bit Quadrature Digitizer
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.75V to 5.25V, TA = +25C, unless otherwise noted.) PARAMETER Power Detect Output Minimum Power Detect Output Maximum ADC LSB Size ADC Amplitude Response Match ADC Input Offset ADC Differential Nonlinearity ADC Integral Nonlinearity RF Signal Path DC Gain Composite I/Q Gain Mismatch Buffered Reference Voltage (Zero Temperature Coefficient) Buffered Reference Voltage (Proportional to Absolute Temperature) VPTAT Temperature Coefficient Buffered Reference Voltage (2 x VREF) Data Output High (Note 3) Data Output Low Data Output Source Current (Note 3) Data Output Sink Current Data Clock Output High (Note 3) Data Clock Output Low Data Clock Output Source Current (Note 3) Data Clock Output Sink Current Master Clock Input Dynamic Range Master Clock Input Resistance Master Clock Input Capacitance Reference Clock Output High (Note 3) Reference Clock Output Low Reference Clock Output Source Current (Note 3) Reference Clock Output Sink Current Digital Input High Threshold (Note 5) Digital Input Low Threshold (Note 5) Digital Input Current High (Note 5) Digital Input Current Low (Note 5) FLTRSEL Input Current High FLTRSEL Input Current Low V2R5 VOH VOL IOH IOL VOH VOL IOH IOL PMCLK RIMCLK CIMCLK VOH VOL IOH IOL VIH VIL IIH IIL IIH IIL VIH = 2.0V VIL = 0.8V VIH = 2.0V VIL = 0.8V 0.8 -150 -400 -500 -790 RL = 10M, CL = 15pF RL = 10M, CL = 15pF RL = 1M, CL = 15pF, VO = 2.4V RL = 1M, CL = 15pF, VO = 0.5V 400 50 2.0 2.2 0.5 SYMBOL VPWR VPWR LSB AVM VOFFAD DNL INL AVRF M(IQ) VREF AGC set to maximum gain Entire signal path, DC, VFTUNEI = VFTUNEQ = V2R5 RL = 1k, CL = 0.1F RL = 40k, CL = 0.01F TA = 0C to +70C Ratio of V2R5 to VREF RL = 1M, CL = 15pF RL = 1M, CL = 15pF RL = 1M, CL = 15pF, VO = 2.4V RL = 1M, CL = 15pF, VO = 0.5V RL = 1M, CL = 15pF RL = 1M, CL = 15pF RL = 1M, CL = 15pF, VO = 2.4V RL = 1M, CL = 15pF, VO = 0.5V RL = 50 external, f = 5MHz 400 50 0 2 5 10 400 50 2.2 0.5 1.9 2.2 0.5 TA = +25C TA = 0C to +70C (Note 2) 1.18 1.0 0.9 4.5 2.1 63 0.5 1.25 1.3 1.5 V mV/C V V V A A V V A A dBm k pF V V A A V V A A A A Channel to channel LSB = 24mV, either channel CONDITIONS VOBB = 0Vp-p VOBB > 2V DC 3.75 21 25 0.4 0.5 1.0 1.0 MIN TYP MAX UNITS 1.5 V V mV dB LSB LSB LSB dB dB V
MAX2101
VPTAT
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3
6-Bit Quadrature Digitizer MAX2101
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.75V to 5.25V, TA = +25C, unless otherwise noted.) PARAMETER IF Port Dynamic Range (Notes 2, 6) IF Port VSWR (Note 6) IF Input Frequency Range Noise Figure (Note 6) Noise Figure Variation SYMBOL PIF VSWR fIF NF NF CONDITIONS RS = 50, fIF = 400MHz to 700MHz RS = 50, RTERM = 25, no matching network, fIF = 400MHz to 700MHz (Note 2) RTERM = 50, gain configured for PIF = -50dBm Maximum gain to minimum gain Gain configured for PIF = -10dBm, fBB1 = 5MHz, fBB2 = 6MHz Gain configured for PIF = -50dBm, fBB1 = 5MHz, fBB2 = 6MHz External resonator, guaranteed 10MHz off fC, 1Hz bandwidth 10kHz off fC, 1Hz bandwidth (limited by external tank Q) 5Hz to 20MHz f = 2 x fC (with respect to signal level at f = 0.5 x fC) fC = 10MHz fC = 30MHz fLO = 650MHz fLO = 650MHz 100Hz to 15MHz, each channel excluding filter (Note 2) fS = 60Msps Full-scale transition, settle to within 1% VBASEBAND = 3Vp-p fIN = 15MHz, fS = 60Msps, VIN = 95% FS f1 = 10MHz, FS - 7dB; f2 = 12MHz, FS - 7dB 60 80 10 10 5.5 -38 1.5 2.3 0.3 1.5 0.5 20 400 -140 -88 0.4 28 2.1 2.9 400 20 1 6 dBm -34 700 MHz dBc/Hz dBc/Hz dB dB V dB degree ns MHz Msps ps ns ns Bits dBc MIN -50 1.7 700 MHz dB dB/dB TYP MAX UNITS -10 dBm
AC SPECIFICATIONS (GND = System Ground, VCC = VCCD = 5.0V 5%)
Input 3rd-Order Intercept Point
IIP3
LO Frequency Coverage LO Device Phase Noise Floor LO Device Phase Noise MIXER Output Baseband Gain Flatness Lowpass Filter Stop-Band Attenuation Lowpass Filter Tune Voltage Composite I/Q Amplitude Balance Composite I/Q Phase Balance Composite Group Delay Variation ADC 0.1dB Bandwidth ADC Maximum Sample Rate, Each Section ADC Aperture Uncertainty ADC Transient Response Baseband Overdrive Recovery ADC Effective Number of Bits ADC Input IP3 Rejection Note 2: Note 3: Note 4: Note 5: Note 6:
fLO N N AV ASB VFTMIN VFTMAX M(IQ) (IQ) T BW0.1dB SRMAX tAU tTRAN Recover ENB IIP3AD
Guaranteed by design. A warm-up of 10 seconds is required at TA = 0C. Sample characterization at TA = 0C to +70C. Digital inputs include Programmable Sample Rate Control (S0-S2), Binary Enable (BINEN). RS = Source Resistance of signal source driving IF input (IFIN, pin 90). RTERM = Termination Resistance for inverting IF input (IFINB, pin 91).
4
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6-Bit Quadrature Digitizer
TIMING CHARACTERISTICS
(VGND = system ground, VCCA = VCCD = 5.0V 5%, TA = +25C, unless otherwise noted.) (Note 4) PARAMETER Data Clock Period (Figure 2) Propagation Delay, Clock to Data (Figure 2) Data Output Skew (all 12 outputs) Settled within 20% (Figure 2) Aperture Delay Relative to Data Clock (Figure 2) Aperture Delay Match, Channel to Channel Data Output Rise, Fall Time (20% to 80%) (Note 7) Data Clock Output Rise, Fall Time (20% to 80%) (Note 7) Reference (Div 6) Clock Output Rise, Fall Time (20% to 80%) (Note 7) Reference Clock Output Jitter, RMS VCO Prescaler Output Rise, Fall Time (20% to 80%) (Note 7) Note 7: RL = 1M, CL = 15pF SYMBOL tPC tPCQ tSKEW tAPERTURE tAP-MATCH tr, tf tr, tf tr, tf tj tr, tf MIN TYP 16 4 1 1 20 4 3 5 30 3 MAX UNITS ns ns ns ns ps ns ns ns ps ns
MAX2101
__________________________________________Typical Operating Characteristics
(VCC = 5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2101-TOC 01
SUPPLY CURRENT vs. TEMPERATURE
MAX2101 TOC 02
VREF (PIN 88) VOLTAGE vs. TEMPERATURE
MAX2101 TOC 03
260 255 250 ICC (mA) 245 240 235 230 4.75 4.85 4.95 5.05 5.15
300 290 SUPPLY CURRENT (mA) 280 270
1.220 1.218 1.216 VREF (V) 1.214 1.212 1.210 1.208 1.206
260 250 240 230 220 210 200
5.25
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
VCC (V)
TEMPERATURE (C)
TEMPERATURE (C)
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6-Bit Quadrature Digitizer MAX2101
____________________________Typical Operating Characteristics (continued)
(VCC = 5V, TA = +25C, unless otherwise noted.)
VREF (PIN 88) VOLTAGE vs. SUPPLY VOLTAGE
MAX2101 TOC 04
VPTAT (PIN 97) vs. TEMPERATURE
MAX2101 TOC 05
VPTAT (PIN 97) VOLTAGE vs. SUPPLY VOLTAGE
1.18 1.16 1.14 VPTAT (V) 1.12 1.10 1.08 1.06 1.04 1.02
MAX2101 TOC 06
1.215
1.4 1.3 1.2 1.1 1.0
1.20
1.214
VREF (V)
1.213
1.212
1.211
VPTAT (V)
0.9 0.8 4.85 4.95 5.05 5.15 5.25 0 10 20 30 40 50 60 70 VCC (V) TEMPERATURE (C)
1.210 4.75
1.00 4.75 4.85 4.95 5.05 5.15 5.25 VCC (V)
PWR (PINS 85, 96) VOLTAGE vs. BASEBAND AMPLITUDE
4.0 3.5 3.0 PWR (V) 2.5 2.0 1.5 1.0 0.5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 BASEBAND AMPLITUDE (V) TA = +25C
MAX2101 TOC 07
4.5 TA = +70C
DIFFERENTIAL LINEARITY vs. ADC CODE
MAX2101 TOC 10
ADJ CODE DELTA ERROR (LSB)
100m 50m 0 -50m -100m -150m ADJ CODE DELTA ERROR (LSB) vs. CODE DNL = 0.173 LSB 5 10 15 20 25 30 35 40 45 50 55 60
CODE
6
_______________________________________________________________________________________
6-Bit Quadrature Digitizer
____________________________Typical Operating Characteristics (continued)
(VCC = 5V, TA = +25C, unless otherwise noted.)
MAX2101
INTEGRAL NONLINEARITY vs. ADC CODE
MAX2101 TOC 11
100m 50m ERROR (LSB) 0 -50m -100m -150m ADC ERROR (LSB) vs. CODE INL = 0.15 LSB
5
10
15
20
25
30
35
40
45
50
55
60
CODE
RF SIGNAL PATH GAIN vs. AGC (PIN 93) VOLTAGE
MAX2101-TOC 12
INPUT IP3 vs. IF POWER
5 0 IIP3 (dBm) -5 -10 -15 -20 -25 -30 P(BB1) = P(BB2) = -16dBm @ P(FSIN) = -10dBm P(BB1) = P(BB2) = -56dBm @ P(FSIN) = -50dBm -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 IF POWER (dBm) fLO = 668MHz fBB1 = 5.1MHz fBB2 = 6.1MHz fC = 10MHz
MAX2101-TOC 13
INPUT IP3 vs. FILTER CUTOFF FREQUENCY
8 7 IIP3 (dBm) 6 5 4 3 2 1 0 5 10 15 20 25 30 35 CUTOFF FREQUENCY (MHz) fLO = 464MHz or 668MHz fBB1 = 5.1MHz fBB2 = 6.1MHz P(BB1) = P(BB2) = -16dBm P(FSIN) = -10dBm
MAX2101-TOC 14
60 50 40 GAIN (dB) 30 20 10 0
10
9
fLO = 624MHz fBB = 5.1MHz
-35 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VAGC (V)
NOISE FIGURE vs. IF INPUT POWER
MAX2101-TOC 15
IFIN (PIN 90) VSWR vs. FREQUENCY
1.9 1.8 1.7 IFIN VSWR 1.6 1.5 1.4 1.3 1.2
MAX2101-TOC 16
30 28 26 NF (dB) (DSB) 24 22 20 18 16 14 12 10 -55 fLO = 624MHz fBB = 10MHz -50 -45 -40 -35
2.0
1.1 1.0 -30
RS = 50 (PIN 91) IFINB AC TERMINATED IN 25 200 300 400 500 600 700 800 900
IF POWER (dBm)
FREQUENCY (MHz)
_______________________________________________________________________________________
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6-Bit Quadrature Digitizer MAX2101
______________________________________________________________Pin Description
PIN 1, 9, 12, 13, 18, 19, 63, 67, 82, 83, 89, 92, 98, 99 2 3 4 5 6 7 8 10 11 14 15 16 17 20, 21 22, 59 23 24 25, 29, 38, 40, 44, 52 26 27 28 30, 37, 43, 51, 55 31 32 33, 48 34, 47 8 NAME FUNCTION PIN 35 36 GND Ground 39 41 42 VGNDQ BBINQ FTUNEQ OFFQ BBOUTQ BBOUTQB VCCQ VGNDP VCCP TNKB VCC2 VGND2 TNKA VGNDAD VSUBAD VCOPRE VCOPREB Q Channel Baseband Ground Q Channel Baseband Amplifier, External Input Q Channel Filter Cutoff Frequency Control Q Channel Baseband Amplifier Offset Adjust Q Channel Baseband Amplifier Output Q Channel Baseband Amplifier Inverted Output Q Channel Baseband +5V Supply Prescaler Ground Prescaler +5V Supply Oscillator Resonator Port Oscillator +5V Supply Oscillator Ground Oscillator Resonator Port A/D Converter Ground A/D Converter Substrate Divide-by-16 Prescaler Output Divide-by-16 Prescaler Complementary Output Digital Output +5V Supply 72 VGNDO D5Q D4Q VGNDO D3Q D2Q VCCD VGNDD Digital Output Ground Q Channel Data Output, bit 5 (MSB) Q Channel Data Output, bit 4 Digital Output Ground Q Channel Data Output, bit 3 Q Channel Data Output, bit 2 Digital Logic +5V Supply Digital Logic Ground 77 FTUNEI 73 74 75 76 CIB VCCI BBOUTIB BBOUTI OFFI 70 71 VCCO CQ CI 69 CQB 62 64 65 66 68 S0 VCCC MCLK VGNDC ENOPB 45 46 49 50 53 54 56 57 58 60, 61 NAME D1Q D0Q RCLK DCLKB DCLK D0I D1I D2I D3I D4I D5I BINEN S2 S1 VCCAD FUNCTION Q Channel Data Output, bit 1 Q Channel Data Output, bit 0 (LSB) Reference Clock, divide by six from master clock (MCLK) Data Clock Complementary Output Data Clock Output I Channel Data Output, bit 0 (LSB) I Channel Data Output, bit 1 I Channel Data Output, bit 2 I Channel Data Output, bit 3 I Channel Data Output, bit 4 I Channel Data Output, bit 5 (MSB) Binary Enable Programmable Sample Rate Control Input, bit 2 (MSB) Programmable Sample Rate Control Input, bit 1 A/D Converter +5V Supply Programmable Sample Rate Control Input, bit 0 (LSB) Clock Buffer +5V Supply Master Clock Clock Buffer Ground Offset Correction/Enable Correction Inverting Input Q Channel Offset Correction Noninverting Input Q Channel Offset Correction Noninverting Input I Channel Offset Correction Noninverting Input I Channel Offset Correction I Channel Baseband +5V Supply I Channel Baseband Amplifier Inverted Output I Channel Baseband Amplifier Output I Channel Baseband Amplifier Offset Adjust I Channel Filter Cutoff Frequency Control
_______________________________________________________________________________________
6-Bit Quadrature Digitizer
_______Pin Description (continued)
PIN 78 79 80 81 84 85 86 87 88 90 91 93 94 95 96 97 100 NAME BBINI VGNDI VREFIN MIXOUTI VSUBRF PWRI 2R5 VCCIF VREF IFIN IFINB AGC VGNDIF FLTRSEL PWRQ VPTAT MIXOUTQ FUNCTION I Channel Baseband Amplifier, External Input I Channel Baseband Ground High Impedance, connect to VREF (pin 88) I Channel Mixer Output RF Demodulator Substrate I Channel Power Indicator 2x VREF Output IF Signal Processing +5V Supply Bandgap Reference Voltage Output IF Amplifier Noninverting Input IF Amplifier Inverting Input Automatic Gain Control Input IF Signal-Processing Ground Baseband Signal Path Select Q Channel Power Indicator PTAT Reference Voltage Output Q Channel Mixer Output
Each baseband is filtered by an internal 5th-order Butterworth lowpass filter. The on-board lowpass filters have an externally variable bandwidth of 10MHz to 30MHz. Each baseband is then converted by a 6-bit analog-to-digital converter (ADC). The conversion result is stored in a register and is output using the data clock. See Figure 2 for the relation between baseband signal, sample and data clock, and digitized data. The external master clock is internally divided by six and is available at RCLK for external system functions, frequency synthesizers, etc. See Figures 3 and 4 for functional diagrams.
MAX2101
IF Input Port (IFIN, IFINB)
The MAX2101 provides a balanced IF input. The inputs are self-biasing, so the input signals should be AC terminated, depending on system requirements. To minimize noise, the unused input should be AC terminated with 25. To minimize distortion, AC terminate the unused input with a 50 resistor.
VCO Resonator Tank Ports (TNKA, TNKB) and Prescaler
The MAX2101 integrates a negative impedance oscillator with balanced inputs. Use a parallel tank network, as shown in Figure 5. The phase-noise performance of the oscillator near the carrier is dominated by the resonant network. The resonant inductor must have a sufficiently high Q and a self-resonant frequency (SRF) that is more than twice the intended LO frequency. Be sure to minimize parasitic elements surrounding the tank network by using proper layout techniques. See the Applications Information section. The VCO prescaler output provides phase-lock loop capability for controlling the VCO frequency. The prescaler generates the VCO frequency divided by 16. As a result, the prescaler delivers a 25MHz to 43.75MHz signal over the VCO operating frequency range of 400MHz to 700MHz. The differential outputs should have equivalent termination.
______________Detailed Description
The MAX2101 6-bit quadrature digitizer solves one of the most challenging problems of high dynamic range digital-receiver design by combining quadrature demodulation and analog-to-digital (A/D) conversion in a single device. The MAX2101's unique RF-to-Bits function bridges the gap between RF downconverters and CMOS digital signal processors (DSPs). Figure 1 is a simplified connection diagram. The MAX2101 accepts input signals from 400MHz to 700MHz and applies gain depending on the input amplitude. The signal is then split and downconverted to baseband by two mixers, which are driven by two local oscillator (LO) signals in quadrature. An internal voltage-controlled oscillator (VCO) feeds the two LOs.
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9
6-Bit Quadrature Digitizer MAX2101
VCC
1k 68 95 56 62 58 57 0.1F MCLK 65 I CHANNEL POWER-DETECT OUTPUT 10k 0.01F D5I 54 53 D4I 50 D3I 49 D2I 46 D1I 45 D0I I CHANNEL DATA OUTPUT DCLK 80 20k VREFIN DCLKB 42 41 DATA CLOCK 50 MASTER CLOCK INPUT (60MHz)
ENOPB
FLTRSEL BINEN
71 CI VCC GAIN ADJUST 2k 0.01F 50 93 IF INPUT SIGNAL 400MHz to 700MHz 90 0.01F 25 0.01F 88 2.2k 20k 0.1F 4 50 97 91 IFINB AGC IFIN 0.22F 0.22F 76 77 72
S0 S1 S2
CIB OFFI FTUNEI
PWRI
85
VREF VPTAT FTUNEQ
2 0.01F MAX407
1
MAX2101
4k 5.6k 20k
2 MAX407
0.1F
1
5 0.22F 69
OFFQ CQB
D5Q D4Q D3Q
27 28
0.01F
VCC 20k 2k FILTER TUNE
31 32 D2Q 35 D1Q 36 D0Q Q CHANNEL DATA OUTPUT 96 39 17 14 PARALLEL RESONANT TANK (FIGURE 5)
70 0.22F
CQ PWRQ RCLK 10k 0.01F Q CHANNEL POWER-DETECT OUTPUT
23 VCOPRE 24 1000pF PHASE-LOCKED LOOP REFERENCE FREQUENCY INPUT 50 PHASE DETECTOR VCOPREB
TNKA TNKB
LOOP FILTER
Figure 1. Typical Connection Diagram
10
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6-Bit Quadrature Digitizer MAX2101
ANALOG INPUT N N+1 N+2
tAPERTURE tPC DATA CLOCK tPCQ tSKEW DATA OUT NOTE: DATA IS VALID ON THE RISING EDGE OF DCLK. DATA VALID N-1 DATA VALID N
Figure 2. Baseband Signal, Sample/Data Clock, and Digitized Data Timing
OFFI (PIN 76) MIXOUTI BBINI (PIN 81) (PIN 78) 6dB IFINB (PIN 91) AGC 40dB to 0dB 400MHz to 700MHz FTUNEI (PIN 77) 1 0dB LPF 10MHz to 30MHz EN FLTRSEL (PIN 95) 0: INTERNAL 1: EXTERNAL EN LPF 10MHz to 30MHz
0 1
IFIN (PIN 90)
AGC (PIN 93)
CIB (PIN 72)
CI (PIN 71)
150k 150k EN 2
BBOUTI (PIN 75) BBOUTIB (PIN 74)
2:1 0 MUX
0 1
1.5Vp-p (DIFFERENTIAL) BASEBAND CHANNEL I ENOPB (PIN 68) PWRI (PIN 85)
GND: ENABLE VCC: DISABLE PWRQ (PIN 96) 2:1 0 MUX 1 2 90 6dB TNKA (PIN 17) DIV-16 TNKB (PIN 14) 400MHz to 700MHz MIXOUTQ BBINQ (PIN 100) (PIN 3) VCOPRE (PIN 23) VCOPREB (PIN 24) OFFQ (PIN 5) CQB (PIN 69) CQ (PIN 70) FTUNEQ (PIN 4) 150k 150k BBOUTQ (PIN 6) BBOUTQB (PIN 7) 1.5Vp-p (DIFFERENTIAL) BASEBAND CHANNEL Q
0dB 0
EN
Figure 3. Functional Diagram--MAX2101 RF Front-End Section
______________________________________________________________________________________ 11
6-Bit Quadrature Digitizer MAX2101
REFERENCE AMPLIFIER FULL-SCALE/2 VREF ADC 6 DCLK (PIN 42) VREF (PIN 88) SAMPLE-RATE ADJUST BANDGAP REFERENCE VPTAT (PIN 97) DIV 6 RCLK (PIN 39) ADC COMMON MODE FULL-SCALE/2 B/2 REFERENCE AMPLIFIER 6 BINEN (PIN 56) DATA BUFFER 6 DCLKB (PIN 41) MCLK (PIN 65) S0-S2 3 DATA BUFFER B/2 6 D0I-D5I
- BASEBAND CHANNEL I
COMMON + MODE
BASEBAND CHANNEL Q
VREF
D0Q-D5Q
Figure 4. Functional Diagram--MAX2101 ADCs and Supporting Sections
Filter Tuning
The MAX2101 integrates two 5th-order Butterworth lowpass filters for anti-alias filtering of the baseband signal. One filter exists for each of the I and Q channels. The filters' cutoff frequency is set by driving the FTUNE pins, pin 77 (I channel) and pin 4 (Q channel). The user sets the I/Q channel filters independently. Figure 6 shows a typical transfer curve of a filter's cutoff frequency versus FTUNE voltage. The MAX2101's anti-aliasing filtering function provides superior channel-to-channel matching compared to a discrete implementation. The filters are realized using a gyrator topology, which inherently has a strong temperature dependency. The temperature dependency of the filters must be compensated to achieve a consistent filter response over ambient temperature. This compensation is easily summed with the user-supplied filter tune signal, with the techniques discussed for both current-drive and voltage-drive implementations later in this section. Figure 7 shows a typical characteristic of the FTUNE signal required to provide a constant filter cutoff frequency over temperature.
12
V+
RCHOKE 1k CVAR 2pF to 10pF FROM PLL FILTER CVAR 2pF to 10pF CC 470pF 14 LRES 8nH 17 CC 470pF TNKB
RBUF 10k
MAX2101
RBUF 10k CFLTR 0.1F
CSH 3pF to 12pF
TNKA
Figure 5. Typical Parallel Resonant Network
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6-Bit Quadrature Digitizer MAX2101
FILTER CUTOFF FREQUENCY vs. FTUNE
MAX2101 TOC Fig 6
FILTER CUTOFF FREQUENCY TEMPERATURE DEPENDENCE
fC = 15MHz 1.95 1.90 1.85 1.80
MAX2101 TOC Fig. 7
30 TA = +25C CUTOFF FREQUENCY (MHz) 25
2.00
20
15
10
FTUNE (V)
1.75 1.70 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 FTUNE (V) 0 20 40 60 80 100 120 140 TEMPERATURE (C)
5
Figure 6. Typical Filter Cutoff Frequency vs. FTUNE Input Voltage
Figure 7. Typical Filter Cutoff Frequency Temperature Dependence
The MAX2101 provides temperature-compensated bias voltages that, when scaled and summed with the usersupplied filter-control signal, provide the necessary compensation for the filters. The filter-control signal can originate in one of two forms: an analog current, or an analog voltage. The temperature compensation signal will be added to the control signal as discussed below.
Voltage Drive A suggested technique of filter drive uses a voltage source, such as a voltage output DAC. The temperature compensation signals, VPTAT and VREF, are shifted and scaled, then summed with the control voltage, and the sum is applied to the FTUNE inputs. See Figure 8 for a possible implementation. The transfer function for Figure 8's voltage drive configuration can be evaluated as follows:
VTC = VREF + RF (VREF - VPTAT ) R TC RF (VREF - VPTAT ) R TC
Current Drive An alternate form of filter drive uses a current source, such as a current-output DAC. The current is transformed to the appropriate voltage via a transresistance network, which will drive the FTUNE input(s). The temperature compensation signals, VPTAT and VREF, are shifted and scaled, transformed to current, added to the user-supplied current, and the sum is transformed back into the temperature compensated control voltage (Figure 9).
Amplifier U1A generates a shifted reference signal, V TC . V TC is transformed into a current through the resistor RTC . R TC also scales this signal such that, when compared to the feedback resistor RF, the proper temperature dependence is added to the user-supplied filter control current ISET to compensate for the TC of the filter. The expression for the final filter tune signal is expressed as: R VFTUNE = ISET (RF ) + F (VREF - VPTAT ) R TC
VFTUNE = VSET +
Thus, the user-supplied signal VSET, which is characterized by a very small (ideally 0) temperature coefficient, will be summed with a small signal (|VREF - VPTAT| 200mV) whose temperature dependence compensates for the filter's TC.
______________________________________________________________________________________
13
6-Bit Quadrature Digitizer MAX2101
R VREF (PIN 88) R
VSET DACA
R
1 4 MAX418
27
FTUNEI (PIN 77) 0.01F
VREF (PIN 88)
RS 2.2k RTC 5.6k
R
1 4 MAX418
RF 4.7k VREF (PIN 88)
VTC
VPTAT (PIN 97)
R R
R
VSET DACB
R
1 4 MAX418
27
FTUNELQ (PIN 4) 0.01F R = 33k, 1% VCC = 5V
Figure 8. Independent Filter Tune Control Using Two Voltage-Output DACs
RF 4k ISET 0.3mA to 1mA DAC 27 (Q CHANNEL, PIN 4) 0.01F FTUNE (I CHANNEL, PIN 77)
1 2 MAX407
27
VPTAT (PIN 97)
0.01F 33k, 1% 33k, 1% RTC 5k, 1% VTC
1 2 MAX407
VREF (PIN 88) 33k, 1%
VCC = 5V 33k, 1%
Figure 9. Filter Tune Control Using a Single Current-Output DAC
14
______________________________________________________________________________________
6-Bit Quadrature Digitizer
Filter Temperature Compensation In both techniques discussed above, the ratio RF/RTC determines the compensation required to produce a filter response with 0TC. As noted in the VPTAT vs. Temperature graph in the Typical Operating Characteristics, this ratio should be set at 0.8.
by choosing the appropriate value of capacitance, according to the following relation: 1 C= 2fO (150k) where: C = integrator capacitance for cutoff frequency Frequency components of the baseband signal near or below the cutoff frequency will interfere with the operation of this network. Fortunately, the compressed and encoded nature of baseband signals at this stage of the signal chain in typical applications will insure minimal low-frequency components. Hence, this technique will eliminate all offsets, independent of AGC setting, filter cutoff frequency, or changes in ambient temperature. Pin 68, ENOPB, is normally connected to ground. Pulling ENOPB to V CC disables the op amps, thus opening the servo loop, and disabling offset correction. The baseband pins (6, 7, 74, 75) should be left unconnected, or buffered with a high-impedance load (resistive load greater than 10k and capacitive load less than 3pF).
MAX2101
Baseband Offset Correction
The MAX2101 integrates a high level of RF signal processing, and applies substantial gain from the IF inputs to the baseband signals applied to the ADC. Offset in the signal path can seriously decrease the component's dynamic range, and variation in offset between I and Q channels can seriously degrade overall receiver performance. Several circuit design techniques are used to minimize offset within the chip. However, two characteristics of the component contribute to offset in the signal path. The off-chip tank network for the VCO resonates the LO frequency with a relatively large amplitude. If the LO couples into the IF input, the coupled LO will mix down to a DC value, which depends on the AGC setting. This DC signal manifests itself as an offset in the baseband signal. The second source of offset is the active lowpass anti-aliasing filters. This offset depends on the cutoff frequency. These two elements represent the major contributors to DC offset in the signal path.
Sample Clock Generation
The master sample clock (MCLK) input for the MAX2101 is typically driven by a low-noise, low-drift crystal oscillator. The signal should be between 0dBm and +10dBm, and must be AC coupled to the MCLK input. This signal is buffered and divided according to the programmable sample-rate prescaler (PSRP). The actual sample rates are binary weighted divisors of the MCLK frequency. Program the sample rates with pins S0, S1, and S2, as shown in Table 1.
Offset Adjust Pins OFFI, OFFQ
The MAX2101 offers an offset adjust pin for each of the I and Q channels, labeled OFFI and OFFQ, respectively. The offset adjust input exhibits an adjustment range that is sufficient to correct for the errors mentioned above. The polarity of the OFF_ input is such that a positive change of the OFF_ voltage results in a negative transition in the baseband signal, BBOUT_. The offset adjust range compensates for up to 5LSBs of offset. A feedback-controlled, offset-correction network can be realized that will null any offset detected in the baseband signal applied to the ADCs. The differential baseband signal is sampled at the input to the ADC and integrated over a sufficiently large period of time (determined by the minimum frequency of the baseband signal), extracting the offset signal. This error signal is internally applied to the OFF_ input, completing the feedback loop. The MAX2101 integrates the op amps and 150k pickoff resistors of the offset correction network. Figure 10 shows a simplified schematic diagram of the network. Simply connect the appropriate capacitors as shown in Figure 11. The network in Figure 11 is a lowpass filter with a 5Hz cutoff frequency. The user can tailor the cutoff frequency
Table 1. Sample-Rate Control
S2 S1 S0 000 001 010 011 100 101 110 111 Sample Rate fc/ 1 fc/2 fc/4 fc/8 fc/8 fc/16 fc/32 fc/64 Description Full Sample Rate Div-2 Sample Rate Div-4 Sample Rate Div-8 Sample Rate Div-8 Sample Rate Div-16 Sample Rate Div-32 Sample Rate Div-64 Sample Rate
Note: The inputs S0, S1, and S2 are not latched.
______________________________________________________________________________________ 15
6-Bit Quadrature Digitizer MAX2101
72 CIB 76 71 CI 150k 75 5 BBOUTIB 74 220nF OFFQ OFFI 76 220nF
BBOUTI
OFFI 150k
MAX2101
68 ENOPB
CIB CI CQ
72 71 70 69 68 220nF 220nF
MAX2101
150k BBOUTQB 5 OFFQ 150k BBOUTQ 6 7
CQB ENOPB
CQB 69
CQ 70
Figure 10. Offset Correction Network
Figure 11. Offset Correction
Digital Signal Interfacing
The single-ended, LS-TTL compatible data outputs from the ADCs are clocked out with respect to the rising edge of the data clock (DCLK). The output drivers provide sufficient logic levels at speeds up to 60Mbps into a fanout of 1 with a total load capacitance of 15pF. All data outputs should have approximately equivalent loading to ensure proper setup and hold timing. The data clock outputs are also LS-TTL compatible and provide a signal to latch the data at rates up to 60Mbps. The outputs are differential to minimize the harmonic energy that might feed back into the LO or IF inputs. The balanced outputs should have equivalent termination to minimize unwanted EMI. Select either binary or twos-complement output with the binary enable (BINEN) pin. A logic high will select offset binary, and a logic low will select a twos-complement format.
The equivalent input network of the input pins IFIN and IFINB is discussed and illustrated below. However, standard narrow-band impedance matching techniques can be used to improve on this VSWR for the intended IF of the system.
Input Termination Network
The MAX2101 accepts as an input a narrow band IF whose center frequency is located somewhere in the UHF range, between 400MHz and 700MHz. The MAX2101 comprises a significant part of a receiver chain characterized by extremely high dynamic range coupled with demanding intermodulation requirements. As such, it is imperative to provide proper input termination to the MAX2101, to minimize effective VSWR and noise figure at this stage of the system RF signal processing chain. The input of the MAX2101 is designed to deliver a VSWR less than 2:1 over the 400MHz to 700MHz range.
16
Equivalent Input Circuitry The MAX2101's input amplifier is designed to provide a controlled input impedance, provide gain for the signal path, and provide for the component's minimum noise figure. The amplifier uses a feedback topology to provide gain that is insensitive to input frequency, in addition to delivering constant input impedance. Figure 12 illustrates the amplifier's input portion. Ideally, the input amplifier will be designed to match to an anticipated source impedance of 50. The resistive portion of the input impedance at pin IFIN can be approximated as follows: R +r RIN = F E (1 + AV )
where rE is the dynamic resistance at Q3's emitter, and AV is the open-loop gain of the differential-pair amplifier stage. The amplifier can be designed so the frequency response does not appreciably affect the input impedance. Details of the amplifier are left out for simplicity. Figure 12 shows how several parasitic elements contribute to the input impedance over the frequencies of interest. C PAD represents the parasitic capacitance associated with the bond pad and input metallization.
______________________________________________________________________________________
6-Bit Quadrature Digitizer MAX2101
VCC
RI
RI
Q3
Q4
IFIN (PIN 90)
LBW CPAD
RF Q1 RE RE Q2
RF
LBW CPAD
IFINB (PIN 91)
Figure 12. Equivalent Input Network
ZIN ()
At frequencies of interest, CPAD will add a small phase error to the impedance term. The inductance LBW models the bond wire and lead frame in series with the input amplifier. This inductor represents a significant portion of the input impedance, and will contribute the majority of the variation in input impedance as the input frequency is swept from 400MHz to 700MHz. These variables combine to produce an actual input impedance versus frequency (Figure 13). As a result, it is challenging to achieve an extremely low VSWR for the input of a monolithic amplifier, especially over a wide range of frequencies. The MAX2101 provides a VSWR less than 2:1, and delivers this performance over the wide range of anticipated IFs currently considered. Fortunately, for DBS, TVRO, and related applications, the UHF IF is relatively narrow band, allowing the use of standard techniques for narrow-band impedance matching.
IFIN (PIN 90) INPUT IMPEDENCE vs. FREQUENCY
MAX2101 TOC Fig. 15
80 60 RE (ZIN) 40 20 0 -20 -40 200 300 400 500 600 700 800 IM (ZIN)
900
FREQUENCY (MHz) TA = +25C VCC = 5V RS = 50 IFINB (PIN 91) AC TERMINATED IN 25
Narrow-Band Match Many references cover narrow-band matching techniques. The match network synthesis is simplified by assuming the impedance of the source driving the MAX2101's IFIN port is positive, real, and equal to 50. For a given IF, you can simply use a Smith chart to "map" an impedance to the intended source resistance. Using a two-element matching network, you can choose the element next to the input (CSH in Figure 14) to translate the real portion of the impedance to match the source resistance. The second element (LSER in Figure 14) cancels the reactive component of the network (including the effect of CSH), resulting in a real, matched input impedance that provides maximum
Figure 13. Typical MAX2101 IFIN ZIN vs. Frequency (Zs = 50)
power transfer. The transformation uses only reactive elements so that no additional resistive thermal noise is added, which would degrade the noise figure. Figure 14 shows the resulting impedance matching network. The incident signal is AC coupled by CC. LSER and C SH are the matching elements. C SH includes board layout capacitance. The values of these ele17
______________________________________________________________________________________
6-Bit Quadrature Digitizer MAX2101
RS 50 VS (fS = 600MHz) (-47dBm to -7dBm) CC 10nF LSER 8nH CSH 1pF
90
IFIN
MAX2101
91 RTERM 25 CTERM 10nF
IFINB
Figure 14. Example of Input Network to Minimize VSWR and Noise Figure
ments were calculated assuming a 600MHz source frequency. Capacitor CTERM provides an AC termination for the complementary input IFINB. Resistor RTERM provides superior noise figure performance by optimizing the tradeoff between thermal induced noise and the gain of the input amplifier. This network also provides ancillary rejection of out-of-band energy, improving the receiver noise figure and resulting SNR. The topology shown above produces a VSWR less than 1.7:1 over the intended UHF band. Do not DC couple the inputs to ground, as this would result in saturation of the input stage. More elaborate matching networks can be designed depending on the need of the receiver system.
__________Applications Information
Voltage-Controlled Oscillator Equivalent Input Network and Resonator Issues
The MAX2101 performs the quadrature demodulation and digitizing functions within a digital receiver system. A vital component of the quadrature detection function is the generation of a local oscillator (LO) frequency. This signal is typically generated by a VCO controlled by a phase-locked loop. The VCO topology normally used for high dynamic range receivers is the negative resistance amplifier and resonator, due to superior phase-noise performance. The MAX2101 provides the negative resistance amplifier on-chip, and can be easily interfaced with an off-chip resonant network. The MAX2101's VCO amplifier uses a differential topology for several reasons. The differential interface with
18
the resonator network provides superior rejection of spurious signals that might otherwise add to or distort the resulting LO. The differential interface minimizes the effect of parasitic package-related elements that affect the resonant frequency and the loaded Q of the network. The differential-drive network minimizes secondharmonic distortion that might create undesirable mixing products within the signal chain. Figure 15 shows the simplified input network of the negative impedance amplifier, configured as a Wilson oscillator. The amplifier is a simple differential emitter coupled pair with emitter degeneration for controlled open-loop gain. The positive feedback necessary to create the negative input impedance is performed with the feedback capacitors, CF, and the coupling capacitors, CC . The capacitors ensure operation over the intended 400MHz to 700MHz spectrum, and add minimal noise to the system. RB1 provides a proper bias voltage for the capacitors (partially constructed with voltage-dependent pn junctions) and provides for DC interface with a shunting resonant inductor. Note that biasing networks are simplified for brevity. The MAX2101's negative impedance amplifier expects a parallel resonant network. Figure 5 shows an example of a tunable resonant network. The resonator is driven from the phase-locked loop filter output, as noted. The loaded Q of the resonant network, and to a lesser extent the absolute values of the resonant elements, determine the VCO's phase-noise performance. As a result, take care during the design of the resonator to maximize the loaded Q. To achieve the phase-noise
______________________________________________________________________________________
6-Bit Quadrature Digitizer MAX2101
VCC
RI
RI
CF
CC TNKA (PIN 17) RB1 RB2
CF
CC TNKB (PIN 14) RB2 RB1
RE
RE
VB1 IEE
VB2
Figure 15. Simplified Input Network for VCO Resonator Ports
performance in the specification, the resonant network should exhibit a loaded Q greater than 20. The resonating inductor LRES should exhibit as high a Q factor as is reasonably possible. The inductor's selfresonant frequency (SRF) should be well in excess of the intended frequencies of operation. An air-wound design is a simple example of an inductor that would fit these criteria. A dual varactor topology is recommended for CVAR to compensate for the large-signal amplitude incident across the resonator ports. The dual varactor in the arrangement shown in Figure 5 (to first order) allows cancellation of capacitance modulation due to the large signals, as the two diodes are driven in a complementary fashion by the LO signal. The dual varactor design also allows use of devices with larger CO values, simplifying device selection. The varactor should be driven with a large reverse bias to increase the MAX2101's effective Q. The resonant frequency is primarily determined by CSH, which shunts the varactor diodes. CSH is trimmed (selected) to determine the approximate tuning range of the phase-locked loop. For applications relevant to the MAX2101, this frequency range can cover the UHF
spectrum from 400MHz to 700MHz. The varactor within the loop will then determine the actual LO frequency within a much narrower tuning range. Depending on the expected tuning range variation, CSH could be made of a combination of fixed capacitance and trimmed capacitance. This shunt capacitance will increase the loaded Q of the resonator and lower the V to F gain constant, improving the oscillator's phasenoise performance. The coupling capacitors CC couple the variable capacitor network to the tank ports and resonating inductor. These elements should be selected to present low impedance (less than 1) at the lowest expected operating frequency. These capacitors should also exhibit low effective series resistance (ESR) to maintain a high resonator-loaded Q. RCHOKE provides a DC bias for the varactors, while ensuring a high impedance at the intended operating frequency. The magnitude of the choke network's series impedance should be approximately 10 times the resonant inductor's impedance at the operating frequency. Resistors RBUF provide drive for the varactor while ensuring adequate isolation between the two differential resonator ports. CFLTR, in combination with RBUF, provides additional filtering of the drive signal from the loop.
19
______________________________________________________________________________________
6-Bit Quadrature Digitizer MAX2101
DBS System Application
A direct-broadcast satellite (DBS) receiver consists of an antenna to receive the X/Ku band carrier from the satellite, a low-noise block (LNB), an L-band downconverter, and a quadrature demodulator. The system stages include a dual ADC, a matched filter, clock and carrier recovery, error detection and correction, and additional system-dependent DSP. See the Typical Application Circuit on the first page of the data sheet. The LNB provides polar demodulation (vertical and horizontal) and downconversion of the X/Ku band signals to a first intermediate frequency (IF1) in the 950MHz to 2000MHz range. The L-band downconverter converts IF 1 to a second IF (IF 2 ) in the 400MHz to 700MHz range. The MAX2101 performs the next stages as follows: 1) the quadrature demodulator converts IF2 to two baseband signals, I and Q; and 2) the dual ADCs digitize the baseband signals, which are then processed by the various digital blocks to compensate for transmission distortion and to extract the digital baseband data. One interface that causes system designers trouble is the quadrature demodulator to ADC interface. Power is needed to drive the low-impedance interconnect between these two functions. Additionally, this portion of the signal path can introduce phase and amplitude errors that complicate back-end error correction. The integrated MAX2101 solves all of these design problems associated with DBS systems. The MAX2101 combines bipolar technology with excellent RF and data-converter design to integrate the quadrature demodulation and ADC functions. The MAX2101 also includes an IF gain block, a VCO and prescaler necessary to generate an accurate LO frequency, and fully integrated baseband anti-aliasing filters for both I and Q channels. By integrating several functions supporting the quadrature demodulation and A/D block, the MAX2101 replaces several components and eliminates many board-level design and manufacturing problems. board, separate from the active circuitry. Three ground planes should be established, connected at the star ground point. The three ground planes should be dedicated as follows: analog and RF ground plane, digital ground plane, and output ground plane. The various ground pins should be connected to this star ground network according to Table 2. The ground current return path for all supplies should be low impedance at frequencies of interest for each supply.
Table 2. Ground Plane Assignments
Ground Pin VGNDIF VGNDI VGNDQ VGND2 VGNDAD VGNDP VGNDC VGNDD VGNDO Pin Number 94 79 2 16 20, 21 10 66 34, 47 26, 30, 37, 43, 51, 55 Ground Plane analog analog analog analog analog digital digital digital output
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the MAX2101 package. The MAX2101 requires +5V 5% for all supply pins. Bypass the supply pins with high-quality 0.1F and 0.001F ceramic capacitors located as close to the package as possible. The high-frequency supplies, VCCIF and VCC2, both require an additional ceramic surface-mount bypass capacitor nominally valued at 47pF. The baseband supplies (VCCI and VCCQ) need additional filtering to ensure sufficient channel-to-channel isolation. Place a small-value resistor, such as 5, between the supply and the pins to create a single-pole filter with the bypass capacitor. The DC IR drop across the resistor should not exceed 150mV. Alternatively, place an RF choke between the supply and the pins. The SRF of the selected choke must be high enough to block energy from the other baseband channel.
Layout, Grounding, Bypassing
The MAX2101's supply pins are separated to isolate high-current digital noise spikes from sensitive RF and analog sections. All ground potentials must be DC coupled, and resistive drops should contribute no more than 50mV difference between the ground pins. A single-point analog ground ("star" ground point) should be established at the ground supply connection to the PC
20
______________________________________________________________________________________
6-Bit Quadrature Digitizer
____________________________________________________________Pin Configuration
MIXOUTQ
MAX2101
TOP VIEW
FLTRSEL
VPTAT
VGNDIF
PWRQ
VCCIF
VREF
VSUBRF
IFINB
PWRI
GND
GND
AGC
GND
GND
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
2R5
85
84
83
82
GND
IFIN
81 80 79 78 77 76 75 74 73 72 71 70 69 68
GND VGNDQ BBINQ FTUNEQ OFFQ BBOUTQ BBOUTQB VCCQ GND VGNDP VCCP GND GND TNKB VCC2 VGND2 TNKA GND GND VGNDAD VGNDAD VSUBAD VCOPRE VCOPREB VCCO VGNDO D5Q D4Q VCCO VGNDO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MIXOUTI
VREFIN VGNDI BBINI FTUNEI OFFI BBOUTI BBOUTIB VCCI CIB CI CQ CQB ENOPB GND VGNDC MCLK VCCC GND S0 VCCAD VCCAD VSUBAD S1 S2 BINEN VGNDO D5I D4I VCCO VGNDO
MAX2101
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VCCO
DCLKB
VCCD
VCCO
RCLK
D1I
VGNDO
VGNDD
MQFP
______________________________________________________________________________________
VGNDO
VGNDD
D0Q
VCCO
D1Q
VCCD
DCLK
D3Q
D2Q
D0I
D2I
D3I
21
6-Bit Quadrature Digitizer MAX2101
________________________________________________________Package Information
D D1 D3 ZD
DIM INCHES MIN MAX 0.110 0.134 0.010 - 0.100 0.120 0.009 0.015 0.904 0.923 0.667 0.687 0.547 0.555 0.486 REF 0.0256 BSC 0.783 0.791 0.742 REF 0.026 0.037 0.023 REF 0.033 REF 0 7 MILLIMETERS MIN MAX 2.79 3.40 0.25 - 2.55 3.05 0.22 0.38 22.95 23.45 16.95 17.45 13.90 14.10 12.35 REF 0.65 BSC 19.90 20.10 18.85 REF 0.65 0.95 0.58 REF 0.83 REF 0 7
21-7003A
S
0.40 0.016 MIN. R 0.012 E 0.005 E1
E3
DETAIL "A" 0 MIN.
L
PIN #1 ZE
R 0.012 0.005 MIN. 1.6 0.063
DATUM PLANE
5-16
A A1 A2
A A1 A2 B D E E1 E3 e D1 D3 L ZD ZE
A BASE PLANE e B SEATING PLANE
100-PIN MQFP METRIC QUAD FLAT PACK
22
______________________________________________________________________________________
6-Bit Quadrature Digitizer MAX2101
______________________________________________________________________________________ 23
6-Bit Quadrature Digitizer MAX2101
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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